The CGS75 VCS is a licensed adaptation of the Serge DTG/DUSG (Dual Transient Generator/Dual Universal Slope Generator) circuit—the VCS has elements in common with that circuit, but it also incorporates a number of additional features. Tim was intrigued as to how the same few components could act not only to produce slew-limiting/envelope generation, but also perform voltage-following too. It is the aim of this page to describe some of the more interesting aspects of the circuit's operation. (Not included are the more mundane functions, such as the CV-summing etc.—these are fairly standard-fare analogue circuits, descriptions of which abound both in the literature and on the internet.)

Click for the full schematic

Logic/envelope phase switching

The circuit uses LM3900 current-differencing amplifiers (CDAs, also frequently referred to as 'Norton amplifiers') to implement the 'logic' which controls the various phases during envelope generation. To my mind, compared to normal op amps, these have a certain 'inelegance' in their use, and they certainly make frequent appearances in Serge circuits. In the context of the current circuit their use is comparatively simple, so we start with them.

[Negative feedback configurations for op amps are easy because the feedback forces the input voltages to be the same; if negative feedback is applied to a CDA, then it does its level best to keep the currents into the inputs the same. In the absence of negative feedback, the output goes with the biggest input current: more current at the positive input, the output is high; more current into the negative input, the output is low.]

The following scope traces are (note that in this, and all the other scope shots, the vertical scales may be different from trace to trace!): trace 1 (red) is the trigger input (from an LFO); 2 (blue) is the envelope output; 3 (green) is LM3900 pin 9, 'attack'; 4 (orange) LM3900.10, 'not attack'; 5 (mauve) LM3900.4, 'end out':

Considering the LM3900 amplifiers 8/9/13 and 10/11/12 as a pair, the default with no trigger and the envelope low is pin 10 (orange) high (i.e. somewhat below the positive rail), which feeds current into negative input pin 8, which with no trigger/no current into pin 13, the output pin 9 (green) is low (a little above ground). On a trigger input, a pulse of current (larger than that into the negative input) into positive input pin 13 switches output 9 high; with no envelope/little current into positive input pin 12, and now lots of current into negative input pin 11, output pin 10 (orange) goes low (and note that this is unable to impact the state of pin 9, via pin 8). As the envelope climbs to its peak, the current at positive input pin 12 will exceed that into negative input pin 11, and so output 10 switches high, in turn causing output 9 to go low, back to its original state, awaiting another trigger (the exact switch-over point depends on the trimpot setting—my module clearly gives a 6V envelope). Thus pin 9 (green) designates 'attack', and pin 10 (orange) is 'not attack'.

The other trace shown above (mauve) is the 'end out' signal, but note Tim has literally probed pin 4 of the LM3900, so it is bigger than the 5V or so output from the module due to the zener diode. Its default state is high: this feeds about 10μA back to the positive input pin 2, which being more than that into the negative input pin 3 (about 1μA), ensures the output stays high. When the envelope (the 'out' signal) climbs above about 3V, 10μA or more is delivered to the negative input pin 3 (via the 330kΩ), and this will switch the output low, which will stay there whilst there is sufficient current into pin 3. Once the envelope falls back to near ground, all the current into pin 3 is 'robbed' by the 330kΩ resistor, and the output will flip high again—hence the 'end out' signal.

The following traces show the same signals when the circuit is switched into 'cycle' mode, i.e. it acts as an LFO. The cycling is simply achieved by feeding the 'end out' signal back as a trigger, so when end out goes high at the end of the cycle, the whole thing triggers off again for another cycle, ad infinitum. Trace 1 (blue) is the 'envelope' out, i.e. the LFO waveform; 2 (green) LM3900.9 'attack'; 3 (orange) LM3900.10 'not attack'; 4 (mauve) LM3900.4 'end out':

Envelope generation/slew-limiting

At the heart of the circuit is a simple inverting integrator, formed from section 1/2/3 of the TL072, with a 22nF capacitor as the negative feedback loop. Feeding this is a complicated-looking arrangement of four transistors—a pair of NPNs and a pair of PNPs. If these are re-drawn as follows:

it is much clearer that the transistors are merely acting as a pair of differential pairs. The tails of both pairs are wired through the 22kΩ to output pin 7 of section 5/6/7: if, say, pin 7 is negative, then the NPN pair is on, and the PNP pair will be off; Q2 will draw current from the ground at its collector, and Q1 will draw current from the op amp virtual ground at pin 2, so the 22nF charges and the output pin 1 will rise, at a rate depending on the share of current between Q1 and Q2 collectors, which in turn depends on the differential voltage across their bases ('Rise V' and 'Expo V'). If we plot the Q1 and Q3 collector currents, we get the familiar 'tanh' shaped curves we expect of differential pairs (simulation output: sweeping 'Fall V' and 'Rise V'; pin 7 ±10V resp.; 'Expo V' grounded):

If pin 7 is positive, then the PNP pair will be on and the NPN pair off, and now current flows in the opposite direction into the virtual ground, and the charged capacitor will now discharge, causing the output voltage to fall, at a rate this time dependent on the voltage across Q3 and Q4 bases ('Fall V' and 'Expo V'). If all voltages into the transistors are held constant, the current into/out of the integrator is constant, and so the output voltage rises and falls linearly, which is what happens when we are slew-limiting or generating linear envelopes (when the rise and fall pots are pulled, this allows the pin 1 output voltage to impact the voltages at the bases ('Rise V' and 'Fall V' above), hence allowing for exponential- or logarithmic-shaped envelope segments).

When generating an envelope (and not 'following'), section 5/6/7 acts as a basic comparator (as the 47pF acts as an open-circuit—more on this below). The following traces show: 1 (blue) the envelope out ≡ TL072.1; 2 (red) TL072.5; 3 (mauve) TL072.7:

and the envelope generation operation is thus: a trigger in makes LM3900.9 go high, as described above; the PNP connected to LM3900.9 via the 220kΩ/68kΩ is thus turned off, so TL072.5 is pulled to –6V or so by the two 220kΩs on TL072.1; TL072.7 will saturate near the negative rail, so we are in the 'attack' (rise) phase, the NPN pair is turned on, and output pin TL072.1 rises; TL072.5 'tracks' the envelope with an offset—it is negative and increasing; when the envelope gets to 6V, LM3900.10 flips to high (again as above) and LM3900.9 goes low; the PNP turns on, making the diode between the 220kΩs reverse-biased, so now TL072.5 positive input tracks the envelope exactly, which being positive, ensures the output pin TL072.7 goes to nearly the positive rail (we are assuming there is no signal at 'in'), which turns the NPN pair off, the PNP pair on, and so we go to 'not attack' (fall, or decay) phase, and the envelope falls. Finally, when it has fallen far enough, 'end out' goes high, marking the end of the whole cycle. (Note the considerable 'indecision'/oscillation at pin 7 when it has no 'definite' value, as it does during the envelope cycle!)

Voltage follower/slew-limiter

To see how the circuit functions as a voltage follower, let's simplify things a little: from above we know that when we are in 'not attack', LM3900 pin 9 is low, the PNP is on, the diode between the 220kΩs is reverse-biased, and so TL072.5 is only connected to TL072.1 via the 220kΩ resistor; the op amp has negligible input bias current, so we can ignore the 220kΩ and show pins 5 and 1 connected directly; the two differential pairs set-up complicates things too, so let's replace all of that with a simple resistor, R_equiv, say. The circuit we now have to deal with is this:

The operation of the inverting integrator (at right) formed from TL072 1/2/3 is still clear, so now we concentrate on the action of the first amplifier (which, as we mentioned above, sometimes acts as a basic comparator). For the purposes of this analysis, let's assume the non-inverting input (pin 5) is grounded. Then at higher frequencies, the reactance of the 47pF capacitor is negligible when compared to the 10MΩ resistor, and so the whole simply looks like a x100 inverting amplifier (i.e. we get 40dB of gain). At lower frequencies, it is the other way round, the capacitive reactance dominates, so this looks like an inverting integrator with the 0dB frequency given by 1/(2π×47e–12×100e3) = 33.8kHz. The integrator's '1/s' line comes back up from this point at 20dB/decade, meeting the 40dB line at 338Hz, and thus for frequencies above about 300Hz the amplifier gives a gain of 40dB, and for lower frequencies, the gain is even more. The following frequency response shows the overall amplifier response, along with these two other curves, and the TL072/4 open-loop response (which ultimately limits the available gain):

Thus for DC signals the maximum (open-loop) gain of the op amp is available, and hence the assertion that for such signals it acts like a simple comparator is seen to be valid. Replacing this amplifier with a simple gain block 'A_in' results in an arrangement which looks like this:

where now block 'SL' is responsible for the slew-limiting effect. (It is not too difficult to do a slightly more rigorous analysis which shows that this gain approximation still holds even when the non-inverting input is no longer held at ground.) Setting the feedback loop aside for the moment, this bears more than a passing resemblance to the simple integrator/one-pole model often used for a standard op amp:

The transconductance input stage, g_m (a differential pair or the like), feeds an inverting integrator; an inherent characteristic of the g_m-stage—the maximum current it can deliver—imposes the slew-rate limit on the op amp by preventing the integrator output voltage from changing as fast as it would like. The VCS circuit replicates this action, only in this case the slew-rate limit is deliberately imposed by the two differential pairs that constitute the SL block, limiting the current feeding the main integrator (and thus the slew-limiting is determined by the voltages controlling the differential pairs). It is not too difficult to show that this arrangement does indeed give a voltage-follower/unity gain. From the upper diagram the output of the A_in block is
A_in(V_out–V_in) and thus, taking the integrator as –1/(τs),

V_out = –A_in(V_out–V_in)/(τs),

which is easily re-arranged to give

V_out/V_in = A_in/(τs+A_in) = 1/(τs/A_in+1) ≈ 1,

the unity gain we seek, as long as 1>>τ/A_in, i.e. A_in is big and τ is small (τ is the effective time-constant of the integrator, dependent on the 22nF capacitor and the slew-limit current from the differential pairs).

[I have managed to avoid mention of phase and stability considerations in all of the above: suffice it to say that it does just about manage to hang together. Of greatest concern is the phase from the output of the input amplifier, pin 7, back round to its non-inverting input, pin 5; this travels through the main (inverting) integrator, which thus has phase lead of 90°, giving +90° at pin 5; this is halfway between positive feedback (0°) and negative feedback (180°), but as it doesn't seem to be associated with any of the usual detrimental qualities of positive feedback, I'm inclined to regard it as being negative feedback. The input amplifier itself also has large phase changes between working as an integrator at low frequencies, to a straight inverting amplifier higher up.]

The following scope traces are: 1 (blue) sine wave input; 2 (red) the output, when not slew-limiting; 3 (mauve) pin 7, when not slew-limiting; 4 (red) output, when just slew-limiting; 5 (mauve) pin 7, when slew-limiting:

Adding sustain to an envelope

This is achieved by the simple expedient of inputting a pulse of the requisite amplitude into the input whilst an envelope has been triggered—this will cause the envelope to follow the pulse at the appropriate point. In the following: 1 (red), trigger pulse; 2 (blue) ordinary envelope; 3 (blue) sustained envelope; 4 (mauve) sustain pulse at input:

Note that even though the sustain pulse starts during attack, it is ignored, because the LM3900.9 is low, the PNP is on, and the diode between the 220kΩs 'interrupts' the signal from TL072.1 to TL072.5. Once in 'not attack', the envelope will slew down until it reaches the sustain pulse, and then follow it; at the end of the pulse the envelope again slews down normally. The following set of traces shows what happens when the pulse is actually greater than the envelope 6V-point for switching from attack to not attack—it will slew up to the pulse amplitude, and then follow it, again slewing to ground when the pulse finishes: